I2C lockdown NACK fix

Just feel like noting down this issue which has been bugging me since last Thursday afternoon. I had to try and try endless times writing and re-writing the state machines, and scour I2C websites for the solution. Finally, I got it solved after trying out some hints... hope this fix is once and for all~

Issue: When doing a read from EEPROM, the SDA is held low and bus is locked when the first bit of the next data is a 0.

I2C Protocol:

Problem: I2C lockdown
When acting as a master receiver, the I2C spec requires that a NACK be sent by the master upon receipt of the last byte of data from the slave transmitter. This is in order to tell the slave transmitter not to try and send any more data. Otherwise, if the slave tried transmitting more data and the first bit happened to be a 0 you would lock up the bus because the slave would be holding SDA low which would prevent the master from sending the STOP bit! 
(Source: http://processors.wiki.ti.com/index.php/I2C_Tips)

Inspiration to solve the problem:
This is the purpose of the I2C NACK bit that concludes a transfer from the slave IC to the master device. If the master ACKs the last byte and then attempts a STOP condition, the slave might put a 0 on the data line that blocks the STOP condition. If the master NACKs the last byte then the slave IC gives up and everybody exits cleanly.
(Source: http://dangerousprototypes.com/2009/08/17/the-point-of-i2c-nacks/)

While sending the command to read the last byte of data, need to write the NACK command to slave during the same state. (Command register, address <= 3'b100, data <= 8'h28.) Not at the next state machine. And check the NO_ACK_flag asserted high from the EEPROM model side.

OMG... hardware IP is such a nightmare..........................

But finally, I'm a real IC Design Engineer now. Happy~~~~~~~~~ *^^*


leonardlcy said…
good job baby!
家勤 said…
very technical ...

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